High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

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dc.contributor.authorBaysal, Kenan
dc.contributor.authorTaşkın, Deniz
dc.date.accessioned2024-10-29T17:53:18Z
dc.date.available2024-10-29T17:53:18Z
dc.date.issued2023
dc.departmentTekirdağ Namık Kemal Üniversitesi
dc.description.abstractEncryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.
dc.identifier.doi10.35377/saucis...1229353
dc.identifier.endpage217
dc.identifier.issn2636-8129
dc.identifier.issue3en_US
dc.identifier.startpage208
dc.identifier.trdizinid1219593
dc.identifier.urihttps://doi.org/10.35377/saucis...1229353
dc.identifier.urihttps://search.trdizin.gov.tr/tr/yayin/detay/1219593
dc.identifier.urihttps://hdl.handle.net/20.500.11776/13498
dc.identifier.volume6
dc.indekslendigikaynakTR-Dizin
dc.language.isoen
dc.relation.ispartofSakarya University Journal of Computer and Information Sciences (Online)
dc.relation.publicationcategoryMakale - Ulusal Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/openAccess
dc.subjectFPGA
dc.subjectVHDL
dc.subjectmultiplication
dc.subjectlook up table
dc.subjectadder
dc.titleHigh-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier
dc.typeArticle

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