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    Blocking harmful images with a deep learning based next generation firewall
    (Yildiz Technical Univ, 2024) Baysal, Kenan; Taskin, Deniz
    There are various blocking and filtering algorithms for protection against harmful contents on the Internet. However, it is impossible to classify particularly the visual contents according to their genres and block them through traditional methods. In order to block the harmful visual contents, such as various advertisements and social media posts, we need to review and classify them as per their contents. Deep learning method is today's most efficient method to review the visual contents. In this study, only the harmful images were blocked without completely blocking the entire website. Alcoholic drinks were selected as the harmful content data set. For this purpose, a training was provided with 4.6 million images by using CNN (Convolutional Neural Networks) and GoogLeNet architecture. At the end of this training, 97.6469% of accuracy was achieved. F1 score was calculated as 87.75526188% at the end of the test conducted with 154501 images. The images were determined through the network traffic via mitmproxy and classified as harmful or harmless thanks to the trained model, and the filtering process was successfully completed.
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    High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier
    (2023) Baysal, Kenan; Taşkın, Deniz
    Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.