Sneak path current equivalent circuits and reading margin analysis of complementary resistive switches based 3D stacking crossbar memories

Abstract

Sneak path currents of resistive memories is an important issue. They increase with increasing memory size and should be minimized for a usable resistive memory. The complementary resistive cells have been suggested as an alternative to one-cell resistive memories to decrease leakage currents. In literature, multilayer resistive memory topologies have also been inspected to minimize leakage currents. Recently, feasibility of 3D resistive RAMs is also inspected. However, to the best of our knowledge, no one has given equivalent leakage circuit models for complementary resistive switches based 3D resistive RAMs yet. In this study, equivalent leakage circuit models for different layers of a 3D resistive RAM with complementary resistive cells have been given and their leakage resistance and reading margins are compared to that of one layer crossbar memory. Some interesting and crucial results are obtained. Alternative complementary resistive switches based 3D resistive RAM topologies with insulating layer(s) for minimized leakage currents are suggested.